(a) Field of the Invention
The present invention relates to a clock signal generator and, more particularly, to a clock signal generator generally known as a delay locked loop (DLL) that generates an internal clock signal in synchrony with an external clock signal.
(b) Description of Related Art
Recently, it is desired that the data transfer rates increases between integrated circuits. However, the data transfer rate is generally limited by the difference in the propagation rate between an external clock signal and an internal clock signal in each component of an integrated circuit. To circumvent this problem, some proposals have been offered to enable integrated circuits to output data in synchrony with external clock signals by synchronizing the internal clock signal with the external clock signal, even if different propagation delays exist between the data and the control signal for controlling the input/output of the data.
The proposals include employment of a DLL circuit, by which the internal clock signal is generated in synchrony with the external clock. A conventional DLL circuit is described in JP-A-8(1996)-130464, for example. FIG. 1 is a block diagram illustrating the described DLL circuit or clock signal generator.
In the clock signal generator of FIG. 1, a voltage-controlled delay element 1 is used to generate an internal clock signal having a desired phase. A phase comparator 2 detects the phase difference between the external clock signal and the internal clock signal. If the internal clock leads the external clock in phase, an additional delay is provided to the voltage-control delay element 1 by using a control signal supplied from a charge pump 3. On the other hand, if the internal clock lags behind the external clock in phase, the delay by the voltage-controlled delay element 1 is decreased. The amount of the phase shift is determined by a setting of the charge pump 3. Generally, the operational stability of the clock signal generator increases after locking to a desired phase, by slowing the rate of phase shift, however, this takes a longer period (length) of time until the internal clock is locked with the external clock.
The conventional clock generator shown in FIG. 1 requires a maximum time length corresponding to a maximum 180 degrees of a phase shift amount from starting of the operation of the clock signal generator to locking of the internal clock to a desired phase. Reduction of the time length required for the phase shift operation lowers the operational stability of the clock signal generator after locking. Specifically, about 180 degrees/2.5 microseconds are required for the phase shift rate (velocity), which requires as much as about 2.5 microseconds for the internal clock to be locked after the start of, or a standby mode of the clock signal generator.
FIG. 2 shows another conventional clock signal generator using a phase shifter. The clock signal generator comprises the phase shifter 11, a quadrant selector 12, a mixer 13, a phase comparator 14, and a charge pump 15. Referring additionally to FIG. 3 showing a signal timing chart of the clock signal generator of FIG. 2, an external clock signal is supplied to the phase shifter 11 to generate four clock signals including I, Q, I.sub.-- Q, and Q.sub.-- B clocks, each having the same period as the external clock. The phases of these clock signals are such that a phase difference of 90 degrees exists between each adjacent two of the clock signals, as shown in FIG. 3. These four clocks are input to the mixer 13.
The external clock is supplied to the phase comparator 14 to be compared in phase with the internal clock output from the mixer 13. The result of the comparison is supplied to the mixer 13 as well as the quadrant selector 12. The quadrant selector 12 selects signal ISEL or QSEL based on the quadrant switching signal, and the selected signal is supplied to the mixer 13. The selected signal ISEL selects one of the output clocks I and I.sub.-- B from the phase shifter 11 and the selected signal QSEL selects one of the output clocks Q and Q.sub.-- B. In the example of FIG. 3, a clock IJX, obtained by the selection by the select signal ISEL, represents the clock I, and a clock QJX, obtained by the selected signal QSEL, represents the clock Q.
The mixer 13 mixes these two selected signals IJX and QJX by a stepless regulation based on signals supplied from the charge pump 15 to generate a mixed signal JX, which is then amplified by an amplifier, not shown. The amplified signal is output from the clock signal generator as the internal clock signal, which is in synchrony with the external clock signal.
In the conventional clock signal generator of FIG. 2, a lower phase shift rate raises the stability of the clock signal generator after locking of the internal clock to a desired phase, as is the case of the conventional clock generator of FIG. 1, and which involves a similar problem.